The use of Computer Aided design (CAD) tools in the design of application specific integrated circuits (ASICs) is well-known. Despite the use of CAD tools there is still much manual effort in taking a high level specification of an ASIC and producing the detailed physical layout, circuit schematics, and packaging.
These CAD tools have been used to produce programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs). For example, in order to produce the standard STREAM file that is sent to the foundry to produce the FPGA, schematics and layouts are first created manually via a graphics tool. These schematics and layouts are then combined with a FPGA specific cell library using a commercially available Virtuoso custom design platform diagram from Cadence Inc. of San Jose, Calif., to produce the STREAM file (a binary file of the layout in the GDS2 format).
FIG. 1 is a simplified schematic view of a conventional FPGA 48. The FPGA includes a programmable fabric 2 surrounded by an I/O ring 4. The programmable fabric 2 includes configurable logic block (CLB) columns 5, block random access memory (BRAM) columns 6, and a digital signal processing (DSP) column 7. The I/O ring 4 includes input/output blocks (IOBs) and multi-gigabit transceiver (MGT) blocks (not shown). A programmable interconnect structure (not shown in FIG. 1) allows the circuit elements or blocks in the programmable fabric to be interconnected with each other and with the circuit elements or blocks in the I/O ring 4.
Traditionally, the design time to produce the layout, schematic, and package files for FPGA 48 has been relatively long. A modification in the number and type of the columns in the programming fabric 2, or the size of the FPGA or the package type used also required relatively long redesign time.
Thus there is a need for improving the process of producing the detailed physical layout, circuit schematics, and packaging of an IC from a high level specification.